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Features
* Fast Interleave Cycle Time - 35 ns * Continuous Memory Interleaving
- Unlimited Linear Access Data Output
* Dual Voltage Range Operation * * * * * * *
- Low Voltage Power Supply Range, 3.0V to 3.6V or Standard 5V 10% Supply Range Low Power CMOS Operation - 108 mW max. Active at 25 MHz for VCC = 3.6V - 14.4 mW max. Standby for VCC = 3.6V JEDEC Standard Surface Mount Packages - 44-Lead PLCC - 40-Lead VSOP (10 x 14mm) High Reliability CMOS Technology - 2,000V ESD Protection - 200 mA Latchup Immunity RapidTM Programming Algorithm - 50 s/word (typical) CMOS and TTL Compatible Inputs and Outputs - JEDEC Standard for LVTTL Integrated Product Identification Code Commercial and Industrial Temperature Ranges
1-Megabit (2 x 32K x 16) 16-Bit Interleaved Low-Voltage OTP EPROM AT27LV1026 Preliminary
Description
The AT27LV1026 is a high performance 16-bit interleaved low-voltage 1,048,576-bit one-time programmable read only memory (OTP EPROM) organized as 2 x 32K x 16 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode operation.
Pin Configurations
Pin Name A0 - A15 O0 - O15 CS RD ALE PGM NC Note: Function Addresses Outputs Chip Select Read Strobe Address Latch Enable Program Strobe No Connect Both GND pins must be connected. PLCC Top View
O13 O15 VPP VCC ALE A14 O14 CS GND PGM A15 O12 O11 O10 O9 O8 GND NC O7 O6 O5 O4 7 8 9 10 11 12 13 14 15 16 17 42 40 41 39 38 37 36 35 34 33 32 31 30 19 21 23 25 27 29 18 20 22 24 26 28 2 5 3 1 43 6 4 44
VSOP Top View Type 1
A9
A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5
A11 A13 A15 PGM
A10 A12 A14 ALE 4 6 8 10 12 14 16
1 3 5 7 9 11 13 15
2
40 38 36 34 32 30 28 26
39 37 35 33 31 29 27 25
A8 A6 A4 A2 A0 O0 O2 O4 O6
GND A7 A5 A3 A1 RD O1 O3 O5
VCC VPP CS O15 O14 O13 O12
O2 O0 GND A1 A3 O3 O1 RD A0 A2 A4
O11 O10 O9 O8
18 17 20 19
24 23 22 21
GND O7
Rev. 0956D-02/98
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This device is internally architected as two 32K x 16 memory banks, odd and even. To begin a non-linear access NLA cycle, (which typically equals a minimum of two linear access LA cycles), ALE is asserted high and CS is asserted low. The two internal 15-bit counters store the address for the odd and even banks and increment alternately during each subsequent linear access LA cycle. The LA cycle will be terminated when CS is asserted high putting the device in standby mode, or another NLA cycle starts. The LA cycle can be resumed when CS is asserted low and ALE stays low. The AT27LV1026 will continuously output data within each LA cycle which is determined by the read RD signal. Continuous interleave read operation is possible as there is no physical limit to the linear access LA output. When the last address in the array is reached the counters will wrap around to the first address location and continue. For a NLA cycle where A0 = 0 (ALE asserted high, CS asserted low), both even and odd counters will be loaded with new address (A1 - A15). Outputs (O0 - O15) from the even bank will be valid in tACCNLA within the NLA cycle, the outputs from the odd bank will become valid in tACCLA within the following LA cycle while the even counter increments by one to ready the data out for the next LA cycle. The outputs will have even or odd data alternating and the counters increment for the consecutive LA cycles until CS is asserted high putting the device in standby mode, or a new NLA cycle begins. For a NLA cycle where A0 = 1 (ALE asserted high, CS asserted low), the odd counter will be loaded with the new address (A1 - A15) while the even counter gets loaded with
the new address+1. Outputs (O0 - O15) from odd bank of memory will be valid in tACCNLA within the NLA cycle, the data output from the even bank of memory will become valid in tACCLA within the following LA cycle while the odd counter increments by one to ready the data out for the next LA cycle. The outputs will have data from the odd or even memory bank alternately and the counters increment for the following consecutive LA cycles until CS is asserted high putting the device in standby mode, or a new NLA cycle begins. When coming out of standby mode, the device can either enter into a new NLA cycle or resume where the previous LA operation left off and was terminated by standby mode.
System Considerations
Switching under active conditions may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 F high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 F bulk electrolytic capacitor should be utilized, again connected between the V CC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
Operating Table
If A0 = 0 at beginning of NLA cycle:
Consecutive Cycle NLA LA LA LA LA Standby LA LA +1 +1 Counter Even Address +1 +1 Odd Address +1 +1 Outputs from Even Bank from Odd Bank from Even Bank from Odd Bank from Even Bank HiZ from Odd Band from Even Bank
If A0 = 1 at beginning of NLA cycle:
Consecutive Cycle NLA LA LA LA LA Standby LA LA +1 +1 Counter Even Address+1 +1 +1 Odd Address +1 +1 Outputs from Odd Bank from Even Bank from Odd Bank from Even Bank from Odd Bank HiZ from Even Bank from Odd Band
and so on.
and so on.
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AT27LV1026
AT27LV1026
Block Diagram
RD ALE A0 CS PGM
Logic
CLK_ODD Address Input A1-A1 5
CLK_EVEN
Odd Counter
Even Counter
15
15
32K x 16 Memory Array
32K x 16 Memory Array
16 VCC GND VPP
16
MUX 16 CS Data Outputs O0-O1 5
A0
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on A9 with Respect to Ground .......................................-2.0V to +14.0V(1) Note: VPP Supply Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
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Operating Modes
Mode/Pin Non-Linear Access Cycle Linear Access Cycle(2) Standby(2) Rapid Program PGM Verify
(3) (3) (2)
ALE
CS VIL
RD VIL
PGM VIH VIH
A0 VIL/VIH X(1) X VIL/VIH VIL/VIH X VIL/VIH
A1 - A15 Ai X X Ai Ai X A9 = VH (4) A1 - A15 = VIL
VPP X X X VPP VPP VPP VCC
VCC VCC(2) VCC(2) VCC(2) VCC(3) VCC(3) VCC(3) VCC(3)
Outputs DOUT DOUT High Z DIN DOUT High Z Identification Code
VIL X VIH VIH X X
VIL VIH VIH VIL VIH VIL X VIL VIL X X
VIH VIL VIH VIH VIH
PGM Inhibit(3) Product Identification(3)(5) Notes: 1. X can be VIL or VIH.
2. Non-Linear and Linear Access Cycles, and standby modes require, 3.0V VCC 3.6V, or 4.5V VCC 5.5V. 3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V. 4. VH = 12.0 0.5V. 5. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer's Identification word and high (VIH) to select the Device Code word.
DC and AC Operating Conditions for Read Operation
AT27LV1026 -35 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 3.0V - 3.6V 5V 10% -45 0C - 70C -40C - 85C 3.0V - 3.6V 5V 10% -55 0C - 70C -40C - 85C 3.0V - 3.6V 5V 10%
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AT27LV1026
AT27LV1026
DC and Operating Characteristics for Read Operation
Symbol Parameter Condition Min Max Units VCC = 3.0V to 3.6V ILI ILO IPP1 ISB ICC VIL VIH VOL VOH
(2)
Input Load Current Output Leakage Current VPP
(1) (1)
VIN = 0V to VCC VOUT = 0V to VCC VPP = VCC CS = VIH f = 25 MHz, IOUT = 0 mA, CS = VIL -0.6 2.0 IOL = 2.0 mA IOH = -2.0 mA 2.4
1 5 10 4 30 0.8 VCC + 0.5 0.4
A A A mA mA V V V V
Read/Standby Current Standby Current
VCC
VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
VCC = 4.5V to 5.5V ILI ILO IPP1(2) ISB ICC VIL VIH VOL VOH Notes: Input Load Current Output Leakage Current VPP(1) Read/Standby Current VCC(1) Standby Current VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 A 2.4 VIN = 0V to VCC VOUT = 0V to VCC VPP = VCC CS = VIH f = 25 MHz, IOUT = 0 mA, CS = VIL -0.6 2.0 1 5 10 6 50 0.8 VCC + 0.5 0.4 A A A mA mA V V V V
1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP . . 2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP
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AC Characteristics for Read Operation (VCC = 3.0V to 3.6V and 4.5V to 5.5V)
AT27LV1026 Symbol tNLACYC tLACYC tALE tAS tAH tARD tRDL tRDH tACCNLA tACCLA tDF tOH tCS tRC tCR tCA Notes:
(2)(3)
Parameter Non-Linear Access Cycle Linear Access Cycle ALE High Width Address/CS Setup Time Address Hold Time ALE Low to RD Low RD Low Width RD High Width Address to Output Delay in Non-Linear Address Cycle from ALE Low Output Valid Delay in Linear Address Cycle from RD High CS High to Output Float Output Hold from CS High Output Valid Delay from CS Low in Linear Address Cycle RD High to CS Falling Edge Delay CS Falling Edge to RD Low Delay CS Rising Edge to ALE Low Delay 2, 3. - See AC Waveforms for Read Operation.
Condition
Min 70
Typ 80 40
Max
Units ns ns ns ns ns ns ns ns
ALE = CS = VIL
35 7.5 2.5 20 5
ALE = CS = VIL ALE = CS = VIL
13 12 52
ns ns ns ns
ALE = CS = VIL
17 14 0 17 10 12 2.5
ns ns ns ns
AC Waveforms for Read Operation(1)
t ALE
ALE
t
tCA
NLACYC
t AS
CS
t AH
A 0-15
VALID
t RC t CR
t ARD
RD
t LACYC t RDL tACCLA
t RDH
t OH
t DF
t ACCNLA
O
0 -15
NLA
t CS
LA LA LA LA
Notes:
1. 2. 3. 4.
Refer to Test Waveforms and Measurement Levels diagram on next page. This parameter is only sampled and is not 100% tested. Output float is defined as the point when data is no longer driven. When reading a 27LV1026, a 0.1 F capacitor is required across VCC and ground to suppress spurious voltage transients.
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AT27LV1026
AT27LV1026
Input Test Waveforms and Measurement Levels
3.0V 1.5V 0.0V
Output Test Load
tR, tF < 2.5 ns (10% to 90%)
Note: CL = 100 pF including jig capacitance.
Pin Capacitance (f = 1 MHz T = 25C) (1)
Typ CIN COUT Note: 4 8 Max 10 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Programming Waveforms (1)
PROGRAM VIH ADDRESS VIL tAS DATA VIH VIL tDS V CC 6.5V 5.0V DATA IN tDH tDFP ADDRESS STABLE tCS
DATA OUT VALID
READ (VERIFY)
tAH
tVCS
V PP
13.0V 5.0V tPRT VIH tVPS
RD
VIL VIH
ALE
VIL VIH VIL tPW tCSS VIH VIL
PGM
CS
Notes:
1. 2. 3.
The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. tCS and tDFP are characteristics of the device but must accompanied by the programmer. When programming the AT27LV1026 a 0.1 F capacitor is required across VPP and ground to suppress spurious voltage transients.
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DC Programming Characteristics
TA = 25 5C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Limits Symbol ILI VIL VIH VOL VOH ICC2 IPP2 VID Parameter Input Load Current Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Supply Current (Program and Verify) VPP Supply Current A9 Product Identification Voltage PGM = VIL 11.5 IOL = 2.1 mA IOH = -400 A 2.4 50 30 12.5 Test Conditions VIN = VIL, VIH -0.6 2.0 Min Max 10 0.8 VCC + 0.1 0.4 Units
A
V V V V mA mA V
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AT27LV1026
AT27LV1026
AC Programming Characteristics
TA = 25 5C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Limits Symbol tAS tCSS tDS tAH tDH tDFP tVPS tVCS tPW tCS tPRT Notes: Parameter Address Setup Time CS Setup Time Data Setup Time Address Hold Time Data Hold Time CS High to Output Float Delay (2) VPP Setup Time VCC Setup Time PGM Program Pulse Width (3) Data Valid from CS VPP Pulse Rise Time 50 During Programming 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP . Input Rise and Fall Times (10% to 90%) 20 ns Input Pulse Levels 0.45V to 2.4V Input Timing Reference Level 0.8V to 2.0V Output Timing Reference Level 0.8V to 2.0V Test Conditions (1) Min 2 2 2 0 2 0 2 2 45 55 150 130 Max Units s s s s s ns s s s ns ns
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven -- see timing diagram. 3. Program Pulse width tolerance is 50 sec 5%.
Atmel's 27LV1026 Integrated Product Identification Code
Pins Codes Manufacturer Device Type A0 0 1 015-08 0 0 O7 0 0 O6 0 1 O5 0 1 O4 1 0 O3 1 0 O2 1 0 O1 1 0 O0 0 1 Hex Data 001E 0061
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Rapid Programming Algorithm
A 50 s PGM pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 50 s PGM pulse without verification. Then a verification / reprogramming loop is executed for each address. In the event a word fails to pass verification, up to 10 successive 50 s pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is considered failed. After the word verifies properly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails.
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AT27LV1026
AT27LV1026
Ordering Information
tACC (ns) 35 ICC (mA) Active 30 30 45 30 30 55 30 30 Standby 0.1 0.1 0.1 0.1 0.1 0.1 Ordering Code AT27LV1026-35JC AT27LV1026-35VC AT27LV1026-35JI AT27LV1026-35VI AT27LV1026-45JC AT27LV1026-45VC AT27LV1026-45JI AT27LV1026-45VI AT27LV1026-55JC AT27LV1026-55VC AT27LV1026-55JI AT27LV1026-55VI Package 44J 40V 44J 40V 44J 40V 44J 40V 44J 40V 44J 40V Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 44J 40V 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) 40-Lead, Plastic Thin Small Outline Package (VSOP) 10 x 14 mm
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Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
40V, 40-Lead, Plastic Thin Small Outline Package (VSOP) Dimension in Millimeters and (Inches)
JEDEC OUTLINE MO-142 CA
.045(1.14) X 45
PIN NO. 1 IDENTIFY
.045(1.14) X 30 - 45
.012(.305) .008(.203)
.656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4)
.630(16.0) .590(15.0) .021(.533) .013(.330)
.050(1.27) TYP .500(12.7) REF SQ
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
.022(.559) X 45 MAX (3X)
*Controlling dimension: millimeters
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AT27LV1026

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